Contemporary processor architectures define a time-stamp counter (TSC) mechanism to monitor and identify relative time occurrence of processor events. A TSC typically counts the maximum number of guaranteed clock ticks since the most recent central processing unit (CPU) reset. Hence, a TSC is advantageous for system timekeeping and for applications that check time frequently in their operations such as operating systems.
With the increasing use of TSCs, consistent and accurate TSC operations are becoming paramount. To improve consistency and accuracy, some contemporary processors include a TSC in the chipset, from which a counter in a coupled CPU core downloads a value at power transition times. For example, the CPU core can download the chipset TSC count value at wake up times.
However, CPU counters generally operate on a spread, variable (unstable) clock while chipsets generally operate on a non-spread, fixed (stable) clock. This difference leads to counting inconsistencies especially between CPU counters and other counters. For most applications, especially operating systems, this discrepancy and run-time changes of the TSC are not acceptable because the applications use the TSC to compute their respective operating frequencies.
Therefore, the inventor recognized a need in the art for a more reliable time keeping technique in an unstable clock environment.